1. Technical Field
Embodiments of the present invention relate generally to semiconductor circuit technology, and more particularly, to a circuit for calibrating impedance and a semiconductor apparatus using the same.
2. Related Art
Semiconductor packaging is a technology used for the purpose of improving the efficiency of integration. A multi-chip package type in which two or more dies (alternatively, referred to as “chip”) are packaged is prevalent in semiconductor packaging technology.
Each of the dies of the multi-chip package is an independent component. In a case in which each die is a memory device, such as dynamic random access memory (DRAM), each memory device requires an impedance calibration block designed to perform an operation (hereinafter, referred to as “impedance calibration operation”) of accurately matching signal input/output impedance to a target value.
FIG. 1 is a block diagram of a semiconductor apparatus 10 in the related art.
The semiconductor apparatus 10 shown in FIG. 1 includes two dies DIE1 and DIE2.
Impedance calibration block 20 and impedance calibration block 30 are provided in DIE1 and DIE2, respectively.
Each of the impedance calibration blocks 20 and 30 requires a reference resistance having a target impedance value in order to perform the impedance operation.
Process/voltage/temperature (PVT) variation of the die can adversely affect the impedance calibration operation. Therefore, the impedance calibration blocks use resistance arranged outside of the die (hereinafter, referred to as “external resistance”) as the reference resistance in order to perform an accurate impedance calibration operation against variation in the process/voltage/temperature (PVT) in the dies.
As shown in FIG. 1, the two dies DIE1 and DIE2 are coupled to separate external resistances RQ0 and RQ1 through external resistance connection electrodes ZQ0 and ZQ1, respectively.
However, a drawback of the semiconductor apparatus configured with external resistance is the increased circuit area occupied by the resistance device and the additional component, such as a line, for connecting the external resistance to its corresponding die, thereby reducing the layout margin available for the semiconductor apparatus.